- Jobs
ResumeCreate your job-winning resume using our free resume builder.
PortfolioShowcase your skills and projects with a professional portfolio.ResumeCreate your job-winning resume using our free resume builder.Resume BuilderMake a resume for free.Resume TemplatesAccess our extensive library of professional & ready-to-use templates.Resume ExamplesGet inspired by real resume examples to create your own.Occupation GuideAccess resume writing guides tailored for different professions.Resume HelpGet expert advice on all things resume from our team of recruitment specialists.- ResourcesSuccess StoriesBusiness ExcellenceAbout CakeResumeFeatured Reads
- Hire
- Download our App
CakeResume Talent Search
Advanced filters
On
4-6 years
6-10 years
10-15 years
More than 15 years
Employed
Full-time / Interested in working remotely
4-6 years
南台科技大學
・
化學工程與材料工程學系
材料研發人員 @綠能科技股份有限公司2016 ~ 2017
・
Part-time Worker
Within one year
限公司 八月Present 材料分析、製程改善 製程工程師 • 環鴻科技股份有限公司 二月六月 2023 製程改善 產線問題排除 製程優化 製程分析及改善結果彙整 製程/品保工程師 • 京和科技股份有限公司 一月一月 2023 製程改善 材料分析 台灣微軟內勤業務/授
Part-time / Remote Only
4-6 years
國立海洋大學
・
材料工程學系
機構設計工程師 @怡利電子工業股份有限公司2011 ~ 2020
・
資深機構工程師
Within one year
評估，並且主持設計審查會議，與各相關單位專案負責人說明設計內容與產品製程。 ■ 負責評估機構所需的材料，並進行材料分析與驗證，以利導入生產之用。 ■ 負責確認TFT或電容面板的各項尺寸、製程，確認規格尺寸後導入生產。 ■ 負責更換材料
Employed
Full-time / Not interested in working remotely
More than 15 years
嶺東科技大學
・
視覺傳達設計Employed
Full-time / Interested in working remotely
6-10 years
國立臺灣大學
・
物理/材料/顯微科學
硬體研發主任 @ASUS 華碩電腦股份有限公司2012 ~ Present
・
硬體研發工程師
Within six months
理論模型而達到產品品質與可靠度預測之目的。為因應工作上的需求，自己花了許多下班後的時間在學習半導體物理與材料的分析方法，以彌補專業不足的部分。工作中更應用了本身所具備的電子電路與力學知識在分析法的開法與實驗設
Employed
Full-time / Interested in working remotely
10-15 years
國立台灣大學 (NTU)
・
應用力學研究所
研發 @天心資訊開發股份有限公司台中分公司2011 ~ Present
・
軟體開發工程師
Within one month
反推生產單程式 CTI交換程式 批次修改批號程式 汽車業損益報表 批次修改加班時數程式 食品雲修改程式 製衣業客製程式 圖片比對程式 自動關帳程式(ERP) 特休計算作業 資料分析推薦客戶商品 材料需求分析 工務系統 報工系統 還有很多很多~
Employed
・
Open to opportunities
Part-time / Remote Only
6-10 years
國立台中科技大學
・
統計系Employed
Full-time / Interested in working remotely
6-10 years
Chung Yuan Christian University
・
Electronic Engineering
Active
Active
資深產品工程師 @Dialog Semiconductor 德商戴樂格半導體有限公司台灣分公司2022 ~ Present
・
工程師
Within three months
發表在 IOPscience 期刊 親自進無塵室操作多種 機台完成每道製程，清楚瞭解整套RRAM製程流程技能 半導體製程 半導體物理 半導體材料 電性分析 電性量測(DC/TLP SOA) 良率分析 資料統計分析 風險評估分析及應對策略擬定 BCD 製程 BCD 元件分析 擅長工具 Excel
Employed
Full-time / Interested in working remotely
6-10 years
國立交通大學 National Chiao Tung University
・
電子工程
熱/應力量測分析工程師 @矽品精密工業股份有限公司2017 ~ Present
・
工程師
More than one year
Digital Image correlation/JMP analysis ● 擅長技能 - 熱翹曲分析 /材料結構分析/專案管理/大數據分析 Taichung City, Taiwan 工作經歷 三月Present 熱/應力量測分析工程師 矽品精密工業股份有限公司 主要工作內容: 1.依照需求對產品進行熱翹曲量測作業(新材料導入、NPI、Qual、MP、Monitor
Employed
Full-time / Interested in working remotely
4-6 years
南台科技大學
・
半導體工地主任 @新緯建築開發股份有限公司2018 ~ 2021
・
More than one year
黃義豪 32 彰化人 本人自服完兵役到至今已累積大量營建工程經驗，材料估算、進度控制、品質管控、單價分析、材料用量分析、工地現場管理均已能運籌帷幄，並持續吸收新知識新技巧以因應各種瞬息萬變的任何裝況，且不斷地保持自律以提升個
Full-time / Interested in working remotely
6-10 years
國立台灣科技大學
・
營建工程管理The Most Lightweight and Effective Recruiting Plan
Search resumes and take the initiative to contact job applicants for higher recruiting efficiency. The Choice of Hundreds of Companies.
- Browse all search results
- Unlimited access to start new conversations
- Resumes accessible for only paid companies
- View users’ email address & phone numbers
Search Tips
1
Search a precise keyword combination
senior backend php
2
Use quotes to search for an exact phrase
"business development"
3
Use the minus sign to eliminate results containing certain words
UI designer -UX
Only public resumes are available with the free plan.
Upgrade to an advanced plan to view all search results including tens of thousands of resumes exclusive on CakeResume.
Definition of Reputation Credits
Technical Skills
Specialized knowledge and expertise within the profession (e.g. familiar with SEO and use of related tools).
Problem-Solving
Ability to identify, analyze, and prepare solutions to problems.
Adaptability
Ability to navigate unexpected situations; and keep up with shifting priorities, projects, clients, and technology.
Communication
Ability to convey information effectively and is willing to give and receive feedback.
Time Management
Ability to prioritize tasks based on importance; and have them completed within the assigned timeline.
Teamwork
Ability to work cooperatively, communicate effectively, and anticipate each other's demands, resulting in coordinated collective action.
Leadership
Ability to coach, guide, and inspire a team to achieve a shared goal or outcome effectively.
Professional Background
Current status
Employed
Job Search Progress
Professions
Process Engineer
Fields of Employment
Semiconductor
Work experience
6-10 years
Management
None
Skills
Languages
English
・
Professional
Job search preferences
Positions
工程師
Job types
Full-time
Locations
台灣新竹市
Remote
Interested in working remotely
Freelance
No
Educations
School
國立交通大學 National Chiao Tung University
Major
電子工程
陳嘉豪
資深主任製程整合工程師
- 6年半導體製程經驗
- 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
- 掌管全廠最大量產品BCD
- 成功改善超過40餘起案件
- 完成2項公司A級專案
- 訂定超過60餘項最佳化條件(BKM)
- 熟悉多台機台操作
新竹縣竹北市
+886 0989-929-413
工作經歷
UMC 聯華電子 - 資深主任製程整合工程師
一月 2017 - Present (5年)
- 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
- 負責產品：BCD(全廠最大產量)、Logic
- 工作內容：
- 開發新平台(Platform)
- 改善跨製程問題
- WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
- 監控線上產品
- 導入新產品
- 客戶專案的推動 / 執行
- 回覆客戶問題及處理客訴
- 成就 / 貢獻：
- 成功改善40餘起案子，其中超過20項重大案件
- HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
- 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
- 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
- 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
- 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
- 熟悉多台機台操作
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
- 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定
- 成功改善40餘起案子，其中超過20項重大案件
碩士學歷
Micron 美光科技 - 高級缺陷改善工程師
一月 2016 - 十二月 2016 (1年)
- 負責產品：SI(Silicon interposer)
- 工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作
國立交通大學 - 電子工程學研究所
國立中央大學 - 化學工程與材料工程學研究所
指導教授：侯拓宏, 周正堂 教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程
2012 - 2014
2012 - 2014
技能
- 半導體製程
- 半導體物理
- 半導體材料
- 電性分析
- 電性量測(DC/TLP SOA)
- 良率分析
- 資料統計分析
- 風險評估分析及應對策略擬定
- BCD 製程
- BCD 元件分析
擅長工具
Excel PowerPoint Word
語言
- 中文
- 英文 - TOEIC：760
Jia-Hao Chen
Senior Principal Process Integration Engineer(PIE)
- 6 years' experience in semiconductor field
- Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- In charge of the product BCD with maximum output in the whole factory
- Successfully improved more than 40 cases
- Finished 2 of our company's top projects
- Defined more than 60 best known methods(BKM)
- Specialize in operating numerous equipment
Hsinchu, Taiwan
+886 0989-929-413
Work Experience
UMC - Senior Principal Process Integration Engineer
Jan., 2017 - Present (5 Years)
- Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- Product：BCD(With maximum output), Logic
- Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
- Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
- HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors
- Successfully improved more than 40 cases, including more than 20 serious cases
Micron - Senior Defect Engineer
Jan., 2016 - Dec., 2016 (1 Year)
- Product：SI(Silicon interposer)
- Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
- Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica
Master’s Experience
National Chiao Tung University - Electronics Engineering
National Central University - Chemical and Materials Engineering
Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow
2012 - 2014
2012 - 2014
Skills
- Semiconductor Process
- Semiconductor Physics and Devices
- Semiconductor Materials
- Electrical Analysis
- Electrical Measurement (DC/TLP SOA)
- Yield Analysis
- Data Statistical Analysis
- Risk Assessment and Strategy Formulation
- BCD Process
- BCD Device Analysis
Tools
Excel PowerPoint Word
Language
- Chinese
- English - TOEIC：760
陳嘉豪
資深主任製程整合工程師
- 6年半導體製程經驗
- 負責SAMSUNG、NOVATECH、Dialog、REALTECH等大客戶
- 掌管全廠最大量產品BCD
- 成功改善超過40餘起案件
- 完成2項公司A級專案
- 訂定超過60餘項最佳化條件(BKM)
- 熟悉多台機台操作
新竹縣竹北市
+886 0989-929-413
工作經歷
UMC 聯華電子 - 資深主任製程整合工程師
一月 2017 - Present (5年)
- 負責客戶：SAMSUNG, NOVATECH, Dialog, REALTECH, 致新...等
- 負責產品：BCD(全廠最大產量)、Logic
- 工作內容：
- 開發新平台(Platform)
- 改善跨製程問題
- WAT異常及低良率(Low yield)的分析 / 改善 / 追蹤 / 預防 / 提升
- 監控線上產品
- 導入新產品
- 客戶專案的推動 / 執行
- 回覆客戶問題及處理客訴
- 成就 / 貢獻：
- 成功改善40餘起案子，其中超過20項重大案件
- HVG issue, Optimize DTI process, leakage by frame fail, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void...等
- 參與A級專案"BCD Low Ron元件平台(Platform) 開發"，與先進製程研發部門(ATD)合作改善device leakage及量測DC / TLP SOA
- 完成A級專案"Samsung的客製化需求"，成功開發本廠首顆5K高電阻(HR)元件
- 訂定超過60項最佳化條件(BKM)以強化BCD母廠製程
- 查過無數種WAT SPC alarm，有效的確查出異常原因，維持BCD製程穩定度
- 熟悉多台機台操作
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica...等
- 前3年考績分別拿最好的"S"及2次A+，表現屢獲上司們的肯定
- 成功改善40餘起案子，其中超過20項重大案件
碩士學歷
Micron 美光科技 - 高級缺陷改善工程師
一月 2016 - 十二月 2016 (1年)
- 負責產品：SI(Silicon interposer)
- 工作內容：
- 產品缺陷異常的分析 / 改善 / 追蹤 / 預防
- 跨部門專案的推動 / 執行
- 跨部門合作改善缺陷數量
- 建立缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 成就 / 貢獻：
- 成功解決影響全廠的Wafer edge low yield issue
- 建立部門第一套缺陷判定規範(Defect specification)及缺陷種類資料表(Defect category)
- 熟悉SEM, EDS, Leica機台操作
國立交通大學 - 電子工程學研究所
國立中央大學 - 化學工程與材料工程學研究所
指導教授：侯拓宏, 周正堂 教授
GPA：3.8/4
期刊：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
論文名稱：以快速熱氧化技術製作雙氧化層電阻式記憶體之研究 (Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation)
實驗地點：國家實驗研究院(NARLabs)
成就 / 貢獻：
- 成功做出學界第一個自我整流(Self-rectifying) 及自我限流(Self-compliance)的3D結構RRAM，並發表在IOPscience期刊
- 親自進無塵室操作多種機台完成每道製程，清楚瞭解整套RRAM製程流程
2012 - 2014
2012 - 2014
技能
- 半導體製程
- 半導體物理
- 半導體材料
- 電性分析
- 電性量測(DC/TLP SOA)
- 良率分析
- 資料統計分析
- 風險評估分析及應對策略擬定
- BCD 製程
- BCD 元件分析
擅長工具
Excel PowerPoint Word
語言
- 中文
- 英文 - TOEIC：760
Jia-Hao Chen
Senior Principal Process Integration Engineer(PIE)
- 6 years' experience in semiconductor field
- Responsible for major customers such as SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- In charge of the product BCD with maximum output in the whole factory
- Successfully improved more than 40 cases
- Finished 2 of our company's top projects
- Defined more than 60 best known methods(BKM)
- Specialize in operating numerous equipment
Hsinchu, Taiwan
+886 0989-929-413
Work Experience
UMC - Senior Principal Process Integration Engineer
Jan., 2017 - Present (5 Years)
- Client：SAMSUNG, NOVATECH, Dialog, REALTECH, Global Mixed-mode Technology, etc.
- Product：BCD(With maximum output), Logic
- Job Description：
- Develop new platforms
- Improve cross-process issues
- Analyze / Improve / Track / Prevent WAT abnormalities and low yields
- Monitor products on the production line
- Import new products
- Promote / Execute client’s projects
- Respond to client’s problems and handle client complaints
- Achievement / Contribution：
- Successfully improved more than 40 cases, including more than 20 serious cases
- HVG issue, optimize the DTI process, leakage per shot issue, local failure map, Schottky leakage, metal bridging, donut-like failure map, metal fuse bridging, metal void, etc.
- Participated in the top project “Development of BCD low Ron device platform”, cooperated with Advanced Technology Development(ATD) to improve device leakage and measured DC/TLP SOA
- Finished the top project “Customize for Samsung”, successfully developed our first 5K high resistance resistor(HR)
- Defined more than 60 best known methods(BKM) to strengthen the BCD process
- Investigated countless WAT SPC alarms
- Specialize in operating numerous equipment
- Keithley T300A(2657A), Keithley TLP, Agilent 4156, SEM, EDS, TTOX, ETOX, Leica, etc.
- Got the best "S" and 2 "A+" in the past 3 years respectively, and have earned a lot of recognition from many supervisors
- Successfully improved more than 40 cases, including more than 20 serious cases
Micron - Senior Defect Engineer
Jan., 2016 - Dec., 2016 (1 Year)
- Product：SI(Silicon interposer)
- Job Description：
- Analyze / Improve / Track / Prevent abnormal defects
- Promote / Execute cross-department projects
- Cross-departmental cooperation to improve the defect level
- Establish defect specification / category
- Achievement / Contribution：
- Successfully resolved the wafer edge low yield issue affecting the entire factory
- Established the first defect specification / category in our department
- Expert in operating SEM, EDS, Leica
Master’s Experience
National Chiao Tung University - Electronics Engineering
National Central University - Chemical and Materials Engineering
Advisor：Dr. Tuo-Hung Hou, Dr. Cheng-Tang Chou
GPA：3.8 / 4
Journal：IOPscience - Homogeneous barrier modulation of TaOx / TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
Thesis：Study of Double-layer Resistive Switching Random Access Memory Prepared by Rapid Thermal Oxidation
Laboratory：National Applied Research Laboratories(NARLabs)
Achievement / Contribution：
- Successfully made the first 3D structure RRAM with self-rectifying and self-compliance in academia, and published in IOPscience
- Personally entered the clean room to operate numerous equipment to finish all the processes, very familiar with the entire RRAM process flow
2012 - 2014
2012 - 2014
Skills
- Semiconductor Process
- Semiconductor Physics and Devices
- Semiconductor Materials
- Electrical Analysis
- Electrical Measurement (DC/TLP SOA)
- Yield Analysis
- Data Statistical Analysis
- Risk Assessment and Strategy Formulation
- BCD Process
- BCD Device Analysis
Tools
Excel PowerPoint Word
Language
- Chinese
- English - TOEIC：760