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職場能力評價定義
Tang Chieh-Tse(Tang)
FPGA Engineer
Taipei，TW
- HDL development and verification
- Integrated use of FPGA IP with simulation verification to meet functional requirements
- Xilinx FPGA Application development C-Coding
- build the embedded Linux system (Petalinux)
- System verification project planning and system integration and testing.
Pegatron FPGA Engineer
Taipei，TW
- Blog http://hiyougood.blogspot.com/
- Email [email protected]
- Resume(Ch) https://www.cakeresume.com/kkman00234
Develop skill
- C
- Verilog/VHDL
- C#/C++ /python
Math
- PID Control
- Motion control
- FFT
Platform
- Xilinx vivado/Vitis
- Linux
- 8051/STM32/NRF52
Experience
2023/06 - Present
FPGA Engineer
Pegatron
- HDL development and verification
- FPGA IP Integration.
- Xilinx FPGA Application development C-Coding
- build the embedded Linux system (Petalinux)
2018/9 - 2021/8
National Chung Husing University of EE MS
- The graduation thesis is a wireless bluetooth monitoring system applied to spindle monitoring
- Has taken courses such as VLSI, Verilog, signal processing, etc.
2015/7 - 2023/06
EDM RD Team leader
Excetek
- Working assignment
- MCU,FPGA programming(C, Verilog)
- Windows application dev and maintain(C,C++)
2013/6 - 2015/7
Software engineer
Excetek
- CNC controller maintain(Tool: RTX(windows real-time tool),C/C++
2007 - 2012
National Cheng Kung University of BS
- Graduated from Math department of National Cheng Kung University.
Project experience
Phased array
Proof of concept for phase array by Xilinx soc.
Main job:
- HDL develop and verify.
- FPGA IP Integration.
- Xilinx FPGA Application development C-Coding
- build the embedded Linux system (Petalinux)
- System verification project planning and system integration and testing
EDM controller development
Use MCU, FPGA design low cost machine controller, and it has been sold the world for more than 5 years.
Main job:
- UART、ADC、FLASH application.
- Encoder feedback
- Motion control/PID
- Sparking PWM by FPGA
- Tool: C/C++、Verilog
Side project
Research on Wireless Sensor Module Applied to Machine Tool Spindle Monitoring(thesis)
Use piezoelectric blocks ,hardware circuits and MCU convert cutting chatter signals to Bluetooth packet, receiver get packet and analysis by time domain and freq domain(FFT). Find the chatter characteristics in time domain and freq domain to prediction and prevention.
Job:
- Bluetooth sw and fw integration
- Receiver GNU dev
- Spectrum display function (FFT)
- Tool: github、C、C#
Memory allocator discuss activity
Goal is find good memory allocater for rocket controller in linux. And formal verification discussion.My Job is use test,gcover,memory profile tool to build test process.Verification rocket controller sw and use gcover check coverage.And discussing memory deterministic with team member.
Tool: Linux、github、makefile、C
Tang Chieh-Tse(Tang)
FPGA Engineer
Taipei，TW
- HDL development and verification
- Integrated use of FPGA IP with simulation verification to meet functional requirements
- Xilinx FPGA Application development C-Coding
- build the embedded Linux system (Petalinux)
- System verification project planning and system integration and testing.
Pegatron FPGA Engineer
Taipei，TW
- Blog http://hiyougood.blogspot.com/
- Email [email protected]
- Resume(Ch) https://www.cakeresume.com/kkman00234
Develop skill
- C
- Verilog/VHDL
- C#/C++ /python
Math
- PID Control
- Motion control
- FFT
Platform
- Xilinx vivado/Vitis
- Linux
- 8051/STM32/NRF52
Experience
2023/06 - Present
FPGA Engineer
Pegatron
- HDL development and verification
- FPGA IP Integration.
- Xilinx FPGA Application development C-Coding
- build the embedded Linux system (Petalinux)
2018/9 - 2021/8
National Chung Husing University of EE MS
- The graduation thesis is a wireless bluetooth monitoring system applied to spindle monitoring
- Has taken courses such as VLSI, Verilog, signal processing, etc.
2015/7 - 2023/06
EDM RD Team leader
Excetek
- Working assignment
- MCU,FPGA programming(C, Verilog)
- Windows application dev and maintain(C,C++)
2013/6 - 2015/7
Software engineer
Excetek
- CNC controller maintain(Tool: RTX(windows real-time tool),C/C++
2007 - 2012
National Cheng Kung University of BS
- Graduated from Math department of National Cheng Kung University.
Project experience
Phased array
Proof of concept for phase array by Xilinx soc.
Main job:
- HDL develop and verify.
- FPGA IP Integration.
- Xilinx FPGA Application development C-Coding
- build the embedded Linux system (Petalinux)
- System verification project planning and system integration and testing
EDM controller development
Use MCU, FPGA design low cost machine controller, and it has been sold the world for more than 5 years.
Main job:
- UART、ADC、FLASH application.
- Encoder feedback
- Motion control/PID
- Sparking PWM by FPGA
- Tool: C/C++、Verilog
Side project
Research on Wireless Sensor Module Applied to Machine Tool Spindle Monitoring(thesis)
Use piezoelectric blocks ,hardware circuits and MCU convert cutting chatter signals to Bluetooth packet, receiver get packet and analysis by time domain and freq domain(FFT). Find the chatter characteristics in time domain and freq domain to prediction and prevention.
Job:
- Bluetooth sw and fw integration
- Receiver GNU dev
- Spectrum display function (FFT)
- Tool: github、C、C#
Memory allocator discuss activity
Goal is find good memory allocater for rocket controller in linux. And formal verification discussion.My Job is use test,gcover,memory profile tool to build test process.Verification rocket controller sw and use gcover check coverage.And discussing memory deterministic with team member.
Tool: Linux、github、makefile、C