The compensation package is negotiable and open to discussion during the interviews with SiFive. However, the salary is confidential information at SiFive. 40K+/month is shown here to be in compliance with the law in Taiwan and regulations of CakaResume.

RISC-V is a groundbreaking CPU instruction set architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively run by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon.

As new RISC-V ISA extensions are prototyped, implemented, and standardized, SiFive will remain at the forefront of RISC-V innovation by shipping the highest performance, the lowest power RISC-V processors in the world. In order to achieve this goal, we need specialists in vector extensions. In the SiFive Vector team, you will build the RISC-V vector backend in LLVM (open source) and an AI-specific high-performance library.

The Challenge:

- Compute library optimization

- Co-work with HW members for architecture exploring and tuning

- Deep learning application/middleware integration

- Open-source software development/integration

What you bring to the challenge

- Familiar with C/C++11

- Experience with software performance tuning

- Basic understanding of Deep learning

- Basic understanding of Computer architecture

- Strong interpersonal skills and excellent team collaboration