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Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4.
Linux
UNIX
40K+ TWD / month
3 years of experience required
No management responsibility
Logo of 晶豪科技 ESMT.
1. 設計感測處理器晶片的數位電路: 1) FIR/IIR digital filter design and implementation. 2) 32bit MCU AHB/DMA/UART/I2C/SPI/Timer/RTC/WDT/PIT/GPIO design. 3) digital/analog integration and co-simulation . 4) MAC design and optimization. 5) sensor algorithm development. 2. 開發測試程式: 數位
60K ~ 200K TWD / month
1 years of experience required
No management responsibility
Logo of 台灣電子設計自動化股份有限公司.
TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the
Verilog
SystemVerilog
C/C++
80K ~ 200K TWD / month
5 years of experience required
Managing 5-10 staff
Logo of 浦飛爾科技有限公司.
1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉
780K ~ 2.34M TWD / year
No management responsibility
Logo of Alpha & Omega Semiconductor (Taiwan) Ltd. .
1) DCDC Power IC design 2) Over 3~5 years experience in design house. power management is a must. 3) Review colleague's projects and own projects.
2M ~ 3M TWD / year
No management responsibility
Logo of Ali Tech.
1.Front-End/Modem (Baseband) Architecture Design for WiFi6/BT/BLE systems; 2.Optimization of Frontend/Modem circuits and simulation/verifications; 3.Digital Circuit Design and Verification – RTL Coding/Synthesis/STA/…
C++
FPGA
ASIC
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of Ali Tech.
1.高速介面(SerDes)類比電路設計 2.Circuit design of CTLE/CDR/DFE/PLL/TX 3.Familiar with SerDes and DDR PHY architecture (ex: PCIe3 / USB3 / HDMI2 / DDR4 / LPDDR4/4x ...etc)
C++
FPGA
PLL
1.8M ~ 2.3M TWD / year
No management responsibility
Logo of 通嘉科技 Leadtrend.
【工作內容】 1. 負責類比電源IC之設計/模擬/驗證/除錯 2. 管控類比電源IC之設計/模擬/驗證/除錯..等流程,追蹤相關流程進度 3. 撰寫各設計流程之設計/除錯分析報告 *意
60K+ TWD / month
No management responsibility
Logo of NVIDIA.
We are now hiring for a Senior Mixed-signal Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can
Verilog
Mixed-Signal
PLL
5 years of experience required
No management responsibility
Logo of NVIDIA.
NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ . This
Verilog
TGC Europe
5 years of experience required
No management responsibility

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