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1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh

負責 高速 PLL 以及 Serdes 相關類比電路開發。 設計PCIe/USB/SATA相關APHY serdes電路，例如：USB4、PCIe5、25G serdes

專長是Class D Amp IP設計的類比IC設計人員協助產品研發, 且相關設計/產品經驗有 10 年以上 。 工作內容： 1. 負責HV Class D Amp新產品的評估, 包含前期的面積評估, 製程比較, 2. 以及中期的Class D Amp IP

1. Sensor IC/ Mixed Signal IC Design, Verification, Design/Verification related documents writing: -Familiar with Hspice, Matlab simulation tools. -Familiar with ADC/DAC, Bandgap, Regulator, Filter, and so on related IP design is preferred. -Interesting in Ambient light sensor, Proximity sensor, Long wave length Infrared sensor, Humidity sensor design is preferred. -Familiar with basic semiconductor process is preferred. 2. Support Mass Production Testing 3. Design Document/Report Support

1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus

記憶體電路開發設計(Array, Decoding, Sense Amplifier等電路) 3. 消費性、物聯網與車用電子之非揮發性記憶體電路整合開發設計 --------------------------------------------------------------------------------------------- Our Design Team is responsible for NVM (Non-Volatile Memory) IC circuit design. As an Analog Circuit Design Engineer, your responsibilities include: 1. Design, verify and debug analog circuits ( Bandgap, LDO, Charge Pum

【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.

* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills

Job Responsibilities: Engage in RTL/Digital circuit design, synthesis, and simulation/verification. Conduct FPGA synthesis and verification processes. Manage chip integration, algorithm implementation, and interface design. Generate test patterns.

工作職責 (Responsibilities)： Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. Work with digital team on specification definition Create behavior model for analog/digital evaluation Compliance test for SerDes IP