CakeResume
CakeResume Logo
Se connecter
S'inscrire
Build your Network
My Network
Access your personal network connections and manage your contacts.
CakeResume Meet
Expand your professional network by meeting and connecting with other users.
Community
Engage with other users through discussions, forums, and networking events.
Se connecter
S'inscrire
Avatar of shih-heng sun.
shih-heng sun
Yield Improvement Engineer
ProfileResume
Posts
0Connections
Imprimer
Avatar of the user.

shih-heng sun

Yield Improvement Engineer
TSMC PIE specializing in advanced tech. semiconductor process (3nm~10nm). Well-versed in yield improvement of semiconductor manufacturing process, Logic IC yield analysis, and collaborate with production line to solve problems . Made a huge leap for TSMC advanced IC chip defect detection and yield improvement. Enthusiastic about semiconductor product development and design which can change people's lives.
TSMC Fab12B
National Taiwan University

Professional Background

  • Statut Actuel
    Sans Emploi
  • Profession
    Electrical Engineer
    ・
    Product Engineer
  • Fields
    Électronique Grand Public
  • Expérience professionnelle
    4 à 6 ans (4 à 6 ans pertinente)
  • Management
    None
  • Skills
    Communicating
    Measuring Instruments
    Semiconductor Process
    Property Analysis
    Field Inspection
    Data Analysis
    Word
    PowerPoint
    Excel
  • Languages
    English
    ・
    Courant
    Chinese
    ・
    Natif ou Bilingue
  • Highest level of education
    Master

Job search preferences

  • Desired job type
    Temps plein
    ・
    Intéressé par le travail à distance
  • Desired positions
    Yield Improvement Engineer
  • Lieu de travail désiré
    Taipei City, Taiwan
    ・
    Zhubei, Zhubei City, Hsinchu County, Taiwan 302
  • Freelance
    Je ne suis pas indépendant

Work Experience

Process Integration Engineer

TSMC Fab12B
mai 2019 - déc. 2021
・
2 yrs 8 mos
Hsinchu, Hsinchu City, Taiwan
Proficient in analyzing the relationship between chip electrical properties and process problems. Specialized in using electrical data analysis 3 nm - 5 nm to improve Logic IC performance Experienced in hitherto the most advanced semiconductor process 3 nm .

Yield Improvement Engineer

TSMC Fab12B
août 2016 - déc. 2020
・
4 yrs 5 mos
Hsinchu, Hsinchu City, Taiwan
Expert in most advanced Logic IC process 5 nm - 10 nm and Familiar with advanced measuring instruments SEM, E-beam and Bright/Dark Field Inspection Tool Specialized in detecting defects to improve yield Collaborated with EE & PE to refine Logic IC manufacturing procedure and lower production cost.

Education

National Taiwan University

Master’s Degree
・
M.S. Photonics and Optoelectronics
2013 - 2016

National Taiwan University

Bachelor’s Degree
・
B.S. Physics
2006 - 2010