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Definition of Reputation Credits
張景順 (Peter CHANG)
Photo Process Development Dept.
From 2005 to today, 16 years have been engaged in the industry related to the memory lithography process, from the production line machine program editing to the mask layout design, new material development/process optimization to new product planning/development, has accumulated a considerable amount of Lithography process experience.
Hsinchu, Hsinchu City, Taiwan
工作經歷
Project Manager • 旺宏電子 (MXIC)
1). Development of process scaling conditions and abnormal resolution
NOR Flash: 110/ 75/ 55 nm
NAND Flash: 36 /19 nm
3D NAND Flash: 96L / 192L
2). Survey new materials, tool and software
3). New product mask verification and new process development experiment. (Margin Check)
4). Maintain product yield and solve the problem of low yield by experiment. (Product defect improvement yield increase)
5). The project experiment in the yellow light area and the solution for finding abnormality online.
6).Recipe setting:
Expose: ASML (Dry/ immersion), Canon.
Metrology: CDSEM(Hitachi, Apply) ,Overlay (KLA)
7).Analysis and design for Litho mark .
8).Tool simulation: SMO/PROLITHUS/PRODATA
9).SPIE paper: Reducing the substrate dependent scanner leveling effect in low-k1 contact printing
六月 2010 - 二月 2022
Senior Engineer • 華邦電子 Winbond Electronics Corp.
1). Development of process scaling conditions and abnormal resolution
NOR Flash: 130/90/58 nm
Logic: 180 nm
2). Development and maintenance of SOPs and technical documents related to the yellow light area process.
3). Yellow light area process control (SPC JOB setup, SPC Control)
4). The safety improvement of semiconductor yellow light process.
二月 2005 - 五月 2010
學歷
2002 - 2004
國立中山大學 National Sun Yat-Sen University
化學
技能
- ＋專案策劃
- ＋製程改善
語言
- English — 中階
張景順 (Peter CHANG)
Photo Process Development Dept.
From 2005 to today, 16 years have been engaged in the industry related to the memory lithography process, from the production line machine program editing to the mask layout design, new material development/process optimization to new product planning/development, has accumulated a considerable amount of Lithography process experience.
Hsinchu, Hsinchu City, Taiwan
工作經歷
Project Manager • 旺宏電子 (MXIC)
1). Development of process scaling conditions and abnormal resolution
NOR Flash: 110/ 75/ 55 nm
NAND Flash: 36 /19 nm
3D NAND Flash: 96L / 192L
2). Survey new materials, tool and software
3). New product mask verification and new process development experiment. (Margin Check)
4). Maintain product yield and solve the problem of low yield by experiment. (Product defect improvement yield increase)
5). The project experiment in the yellow light area and the solution for finding abnormality online.
6).Recipe setting:
Expose: ASML (Dry/ immersion), Canon.
Metrology: CDSEM(Hitachi, Apply) ,Overlay (KLA)
7).Analysis and design for Litho mark .
8).Tool simulation: SMO/PROLITHUS/PRODATA
9).SPIE paper: Reducing the substrate dependent scanner leveling effect in low-k1 contact printing
六月 2010 - 二月 2022
Senior Engineer • 華邦電子 Winbond Electronics Corp.
1). Development of process scaling conditions and abnormal resolution
NOR Flash: 130/90/58 nm
Logic: 180 nm
2). Development and maintenance of SOPs and technical documents related to the yellow light area process.
3). Yellow light area process control (SPC JOB setup, SPC Control)
4). The safety improvement of semiconductor yellow light process.
二月 2005 - 五月 2010
學歷
2002 - 2004
國立中山大學 National Sun Yat-Sen University
化學
技能
- ＋專案策劃
- ＋製程改善
語言
- English — 中階