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1.Familiar with RTL design & simulation 2.Familiar with FPGA prototype & emulation 3.Familiar with Verilog coding & ASIC design flow 4.Familiar with Analog and digital co-simulation 5.Familiar with Design documentation 6.Experience in MCU 7.Experience in ADC/DAC is a plus 8.Experience in low poer design flow is a plus 孰悉以下工具: 熟悉 Verilog coding, 與 ASIC design flow 熟悉

1. Verify RTL design with System Verilog and UVM verification methodology. 2. PCIe or USB or SATA related VIP test maintenance and development. 3. Develop verification platform or behavioral models. 4.Test planning, testbench documentation and development.

1.類比IC設計研發 --熟習RS485/RS232/CAN/Digital Isolator IC設計尤佳 2.熟悉ESD/Latchup之設計及防護 3.基本類比IC測試驗證及量產IC經驗

工作內容 Analog & Digital Circuits Design AC/DC,DC/DC power design 使用OrCad 繪製電路圖，DC/DC Power Designing, 設計包含電流自檢, 電壓自檢, OCP, OVP, OTP等電路,電路控制CPLD/FPGA, 負責FCT 專案的研發, Wireless Board 的設計 與客戶溝通達到客戶產品測試

Job Responsibilities: Engage in RTL/Digital circuit design, synthesis, and simulation/verification. Conduct FPGA synthesis and verification processes. Manage chip integration, algorithm implementation, and interface design. Generate test patterns.

工作職責 (Responsibilities)： Build & innovate on high-speed analog/mixed-signal circuits such as PCIe/DDR/HDMI... transmitter and receiver in deep sub-micron CMOS technology for integration in SoC products. Work with digital team on specification definition Create behavior model for analog/digital evaluation Compliance test for SerDes IP

1.Front-End/Modem (Baseband) Architecture Design for WiFi6/BT/BLE systems; 2.Optimization of Frontend/Modem circuits and simulation/verifications; 3.Digital Circuit Design and Verification – RTL Coding/Synthesis/STA/…

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh

尋找一位具有用戶體驗（UX）專長的網站企劃專案經理來帶領我們的網站開發團隊。管理和監控所有的網站開發項目，確保項目按照既定的時間表和預算完成。具有出色的項目管理技巧，能處理複

This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform