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TienYaoHsu
Senior FAE
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TienYaoHsu

Senior FAE
I am confident that the combination of solid engineering background, a variety of practical work experience, and good RTL coding skills has prepared me for being an excellent FPGA engineer. I am responsible for server and switch supporting and help customers survey suitable FPGA for their circuit design.
WEIKENG INDUSTRIAL CO., LTD
National Kaohsiung First University of Science and Technology
台灣新竹市新竹

职场能力评价

专业背景

  • 目前状态
  • 专业
    其他
  • 产业
    硬件
  • 工作年资
    6 到 10 年 (4 到 6 年相关工作经验)
  • 管理经历
  • 技能
    Verilog HDL
    ModelSim
    Xilinx VIVADO
    Lattice Diamond
    Altera Quartus
  • 最高学历
    硕士

求职偏好

  • 预期工作模式
    全职
    对远端工作有兴趣
  • 希望获得的职位
    FPGA engineer
  • 期望的工作地点
  • 接案服务

工作经验

Senior FAE

2016年2月 - 现在
1. Verilog coding/modification for the customer. 2. Function simulation. 3. FPGA engineering support. 4. FPGA board level debug. 5. Familiar with I2C master/slave, UART, PWM, and TACH. 6. Good knowledge of server and switch architecture. 7. The power sequence coding for Intel or AMD CPU/SOC.

Senior Engineer

2013年10月 - 2015年11月
2 年 2 个月
1. Optimization improves the performance of display optical. 2. The peripheral circuit design of the display panel module. 3. Verilog coding. 4. Keil C coding.

Hardware Engineer

2012年10月 - 2013年9月
1 年 0 个月
1. Designing PCB circuit of the Intel x86 platform. 2. To debug the circuit with an oscilloscope.

ZyXEL

2007年4月 - 2010年8月
3 年 5 个月
1. FTTx and DSLAN debugging, troubleshooting and testing. 2. Process and provide RMA services.

学历

Master’s Degree
Computer and Communication Engineering
2010 - 2012
Bachelor’s Degree
Electrical Engineering
2003 - 2005
Associate’s Degree
Electrical Engineering
2001 - 2003