Motivated engineer who is highly energetic, outgoing and tenacity. Have project management experience. Ability to solve problems and rich cost down/capacity max out experience. Co-working with foreigners experience. Quickly learns and masters new concepts and skills.
1.Published Micron internal paper in FY22.
2.TF line yield owner, and scrap wafer improve around 40%.
3.Contact Co/SICONI recipe optimization.
4.Digit line W sputter recipe development for RS reduction.
5.W/SIN capacity improve 5%~8% for max out project.
1.SPC champion, responsible for PVD team meet SPC KPI.
2.Responsible backend layers defect/cost/max out projects.
3.TSV Cu process transfer from JP RD team.
1.Published paper “Capacitance density and breakdown voltage improvement by optimizing the PECVD dielectric film characteristics in metal insulator metal capacitors” in IEEE symposium 2015
2.Responsible for Logic Foundry Thin Film process development