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朱思明
Sr. Engineer
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11Connections
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朱思明

Sr. Engineer
Motivated engineer who is highly energetic, outgoing and tenacity. Have project management experience. Ability to solve problems and rich cost down/capacity max out experience. Co-working with foreigners experience. Quickly learns and masters new concepts and skills.
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Micron Technology 台灣美光
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中原大學 Chung Yuan Christian University
Taichung, 台灣

Professional Background

  • 現在の状況
    無職
  • Profession
    Semiconductor Engineering
    Research / R&D
  • Fields
    半導体
  • 職務経験
    10〜15年 (10〜15年関連の実務経験)
  • Management
    なし
  • Skills
    Word
    Excel
    PowerPoint
  • Languages
    Chinese
    ネイティブまたはバイリンガル
    English
    中級者
    Japanese
    初心者
  • Highest level of education
    Master

Job search preferences

  • Desired job type
    フルタイム
    リモートワークに興味あり
  • Desired positions
    Semiconductor Sr. Engineer, Manager
  • 希望の勤務地
    Taiwan
  • Freelance
    非フリーランス

Work Experience

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OCT CPEE CVD/PVD Sr. Engineer

9月 2022 - 6月 2023
10 mos
Taichung City, Taiwan
Integrate supplier resources to reduce company cost and improve capacity.
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ADTT PVD Sr. Engineer

7月 2020 - 9月 2022
2 yrs 3 mos
Taichung City, Taiwan
1.Published Micron internal paper in FY22. 2.TF line yield owner, and scrap wafer improve around 40%. 3.Contact Co/SICONI recipe optimization. 4.Digit line W sputter recipe development for RS reduction. 5.W/SIN capacity improve 5%~8% for max out project.
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JTC Film Team Sr. Engineer

12月 2018 - 7月 2020
1 yr 8 mos
Taichung City, Taiwan
1.Development Ti/WN/WSI metal sputter recipe for digit line RS reduction 2.New tech process transfer form US RD team.
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PEE PVD Sr. Engineer

7月 2016 - 12月 2018
2 yrs 6 mos
Taichung City, Taiwan
1.SPC champion, responsible for PVD team meet SPC KPI. 2.Responsible backend layers defect/cost/max out projects. 3.TSV Cu process transfer from JP RD team.
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TF Technology Development Engineer

8月 2012 - 7月 2016
4 yrs 0 mos
Hsinchu City, Taiwan 300
1.Published paper “Capacitance density and breakdown voltage improvement by optimizing the PECVD dielectric film characteristics in metal insulator metal capacitors” in IEEE symposium 2015 2.Responsible for Logic Foundry Thin Film process development
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TF Process Engineer

4月 2008 - 8月 2012
4 yrs 5 mos
Hsinchu City, Taiwan 300
1.. NOR/NAND-Flash memory yield and capacity improvement. 2. Thin Film PVD/CVD Process maintenance. 3. CIP competition received Honorable Mention.

Education

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Master’s Degree
物理
2004 - 2006
活動・団体
童軍團, 攝影社,
詳細
“Percolation in Two-dimensional Nanoparticle Films from Colloidal Self-assembly” , 2007 , Physica Status Solidi (a) , vol.204 , p.1856-1862. (SCI期刊)
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Bachelor’s Degree
物理
1999 - 2004
活動・団体
童軍團, 學生會, 吉他社, 國標社