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Logo of Google.
Google welcomes people with disabilities. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Taipei, Taiwan . Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. Experience verifying digital logic at RTL using SystemVerilog for ASICs. Experience verifying digital systems using standard IP componen
Logo of CakeResume Headhunting Recruitment Service.
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh
SystemC
RTL
SOC
3M ~ 4M TWD / year
10 years of experience required
No management responsibility
Logo of Morgan Philips Group.
【工作內容】 1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.
UVM
Verilog
Verification
Regular earnings reach NT$40,000
2 years of experience required
No management responsibility
Logo of 凌耀科技股份有限公司.
1. Sensor IC/ Mixed Signal IC Design, Verification, Design/Verification related documents writing: -Familiar with Hspice, Matlab simulation tools. -Familiar with ADC/DAC, Bandgap, Regulator, Filter, and so on related IP design is preferred. -Interesting in Ambient light sensor, Proximity sensor, Long wave length Infrared sensor, Humidity sensor design is preferred. -Familiar with basic semiconductor process is preferred. 2. Support Mass Production Testing 3. Design Document/Report Support
26.4K ~ 26.4K TWD / month
5 years of experience required
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 10 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience leading a functional verification team for ARM or X86 compliant processor-based products. Experience with functional verification and performance validation of modern mobile processors, micro-architecture, and related technolo
Regular earnings reach NT$40,000
Logo of 台灣電子設計自動化股份有限公司.
TESDA, a fast growing startup is looking for manager with 5+ years experience and 1~5 digital design verification engineers. As a design verification engineer at TESDA, you'll be able to access and verify the design and implementation of hugely complex SoC from world class companies,attractive package and stock options. If you are looking for a position that can offer huge growth opportunity for career and personal finance and work-life balance, TESDA is the
Verilog
SystemVerilog
C/C++
80K ~ 200K TWD / month
5 years of experience required
Managing 5-10 staff
Logo of Foreign Professional Talent Recruitment in Taiwan.
Design and development verification of electric vehicle battery modules and mechanisms. Design and development of structural impact resistance, explosion-proof, waterproof, tolerance analysis, heat dissipation, and series/parallel circuit. Design of plastic injection, sheet metal stamping, aluminum extrusion, aluminum die-casting, welding type products such as resistance welding, arc welding. Research product development trends and formulate new product development strategies. Planning and integ
1.3M ~ 1.5M TWD / year
2 years of experience required
Managing staff numbers: not specified
Logo of CakeResume Headhunting Recruitment Service.
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with FPGA integration, synthesis and verification. 5. Familiar with USB/ High-speed IO related project design is a plus
Digital IC Designer
IC design
Memory
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
Logo of Foreign Professional Talent Recruitment in Taiwan.
DSP firmware development and design. Development and verification of DC-DC digital power converters. Design of voltage/current digital compensators. Firmware driver development for CAN/SPI/UART/I2C, etc. Signal processing.
1.5M ~ 2.5M TWD / year
10 years of experience required
No management responsibility
Logo of 力旺電子 eMemory.
歡迎至力旺招募官網註冊,直接投遞履歷: https://recruit.ememory.com.tw/ 1. 密碼演算法開發 2. 數位電路設計 (RTL) 3. 數位電路驗證 (UVM) 4. FPGA建置整合及驗證 -------------------------------------------------------------------------- 1. Crypto algorithm development 2. RTL design 3. UVM verification 4.
Linux
UNIX
40K+ TWD / month
3 years of experience required
No management responsibility

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